I am passionate about Parallel Programming and Parallel Computer Architecture. Fast computers! I have had the great fortune to help make key contributions to two of the world's fastest computers (#1 on the "Top500" lists many times) and many other supercomputers.
My latest project is Data Parallelism for C++. I am working on a book on Intel's DPC++ compiler, which is Intel's open source SYCL compiler called DPC++. We released the first four chapters for the book in November 2019, and aim to complete the book by mid-2020. We also have developed training for DPC++ available on Intel's web site for oneAPI programmers.
I am working as an independent consultant on parallel computing, high performance computing (HPC, AI, ML, CPUs, FPGAs, GPUs, and accelerators of all kinds). I previously worked at Intel until 2016. During my 10,001 days at Intel, I contributed to many projects including the world's first TeraFLOP/s supercomputer (ASCI Red) and the world's first TeraFLOP/s microprocessor. Today, I continue to publish articles and do consulting in areas related to high performance computing, and applications that use high performance computing including AI/ML.
Passionate about Parallel Programming and Parallel Computer Architecture
I am always looking to improve the methods and tools for Parallel Programming through better models, understanding and training. I have authored/edited to create nine books (so far) reflecting this passion. I have also taught many courses, classes, tutorials, and workshops. I am familiar with many software developer markets from embedded to HPC.
I am a strong communicator, and available to help with...
Created many other blogs, papers, presentations, etc.
Over 30 years in High Performance Computing and Parallel Computing.
Author of nine programming books, numerous papers and blogs.
Expert on Supercomputer architectures and HPC programming.
James Reinders Consulting LLC
August 2016 – present
HPC and ML/AI Consultant
Expert consulting, Blogging, Technical writing, Teaching, White Papers
Pattern Computing, High Performance Machine Learning
Book projects: TBB, FPGA, OpenMP (TBB being published in April 2019)
February 1989 – June 2016
Intel Achievement Award Recipient, Intel’s highest honor.
Parallel Programming Models Architect for Intel’s HPC Business.
Key contributor for two of the longest standing #1 computers in history: ASCI Red (#1 for June 1997-November 2000) and Tianhe-2A (#1 for June 2013-June 2016).
Author/editor of eight technical books (while at Intel, another coming in 2019 post-Intel)
HPC Technical Communications Expert:
Public Face for Intel to High Performance Computing (HPC) Software Developers, Corporate qualified spokesperson for Press and Analysts.
Business Architect of Intel’s Software Tools Business (propelling Intel from obscurity to a leader in software development tools, with a powerful channel and sales force).
Official roles and titles during tenure at Intel:
Parallel Programming Model Architect and Evangelist, Director, October 2010-June 2016.
Evangelist and Director of Marketing & Sales for Software Development Tools, 2000-2010
Technical Marketing and Customer Support Manager – Intel Software Development Tools, Pentium 4 and Itanium Software Development Systems, 1998-2000
Project lead and manager Intel Fortran Compiler and C/C++ Frontend teams, 1995-1998
Senior Systems Architect ASCI Red Project (world’s first TeraFLOP supercomputer), Pentium Pro Compilers, and 64-bit Architecture Pathfinding, 1992-1995
Compiler Engineer and Team Lead, iWarp, Systolic Array Supercomputer, Compiler liaison to Carnegie Mellon University, 1989-1992
Corporate qualified spokesperson (media trained) for Intel, 1998-2016.
Pro TBB: C++ Parallel Programming with Threading Building Blocks, Apress, 2019
Intel Xeon Phi Processor High Performance Programming – Knights Landing Edition, Morgan Kaufmann, 2016
High Performance Parallelism Pearls, Volume Two, Morgan Kaufmann, 2015
High Performance Parallelism Pearls, Volume One, Morgan Kaufmann, 2015
Multithreading for Visual Effects, CRC Press, 2014, co-author with other technical leaders (and friends) from Dreamworks Animation Pixar, AMD, Google, SideFX
Intel Xeon Phi Coprocessor High Performance Programming, Morgan Kaufmann, 2013. Also translated to Japanese (2014) and Chinese (2014).
Structured Parallel Programming, Morgan Kaufmann, 2012. Also translated to Japanese (2013).
Intel Threading Building Blocks – Outfitting C++ for Parallelism, O’Reilly Press, 2007. Also translated to Japanese (2008), Chinese (2009) and Korean (2010). Sole author.
VTune Performance Analyzer Essentials, Intel Press, 2005. Sole author.
Contributor to books
Authored entries on Systolic Arrays and Warp and iWarp, Encyclopedia of Parallel Computing, Padua, David (Ed.), Springer Publishing, 2011.
Author of three chapters in Multi-Core Programming, Akhter, Shameem and Roberts, Jason Gross, Intel Press, 2006.
Author of three chapters in Itanium Architecture for Software Developers, Intel Press, 2000.
Contributor to book iWarp: Anatomy of a Parallel Computing System, Gross, T. and O'Hallaron, D., MIT Press, 1998.
Editor of Intel Parallel Universe quarterly magazine. April 2009 (Issue 1) to Q3 2016 (Issue 25).
Intel whitepapers, blogs and introductory material for publications, 1989-2016.
Hardware and Systems. Reinders, J., in Information Technology Methoden und innovative Anwendungen der Informatik und Informationstechnik, 55(3), pp. 86-90. 2013.
Only the first steps of the parallel evolution have been taken thus far, Reinders, J., Facing the Multicore-Challenge II, Springer, pp1-9, 2012.
Rules for Parallel Programming for Multicore, Reinders, J., Dr.Dobbs Journal, Sept. 5, 2007
Modelling Instruction-Level Parallelism for Software Pipelining, Adl-Tabatabai, A. and Gross, T. and Lueh, G. and Reinders, J., in Proc. IFIP WG10.3 (Concurrent Systems) Working Conf. on Architectures and Compilation Techniques for Fine and Medium Grain Parallelism, pp. 321-330. IFIP WG 10.3,
North Holland, Orlando, FL., Jan 1993.
Intel HPC Developer Conferences 2015: U.S., UK, India, Japan, Korea, China. Overall
technical chair, speaker and MC for U.S.
Intel Developers Forum (IDF), technical presentations every year 2003-2011 and in
2013 and 2015, multiple times “Outstanding Speaker” (top 10). Coaches speakers for most recent IDFs. Also taught courses at IDF events in Beijing, Seoul and Taiwan.
Intel Sales and Marketing Conference (ISMC), United States, more than 10 years as an instructor.
Multicore World, 2012, New Zealand, keynote speaker
LCA2010/Multicore World, New Zealand, keynote speaker
Apple World-Wide Developers Conference (WWDC), San Francisco, invited external speaker, 2007, 2008.
China Software Developers Network Conference, Beijing, invited keynote speaker, 2007.
Evans Data Corporation Developer Relations Conference, San Jose, invited keynote speaker 2009, 2010, 2011.
Microsoft Professional Developer’s Conference (PDC), Los Angeles, invited external speaker and panelist, 2008, 2009.
Finnish Multicore Days 2011 Conference, Stockholm, invited speaker and panelist, 2011.
Swedish Institute of Computer Science, Multicore-Days 2008 Conference, Stockholm, invited speaker, 2008.
Sony Corporation, Annual Technical Summit, Tokyo, invited keynote speaker, 2007.
Customer training – multi-day technical training classes many locations around the world since 1987, hundreds of hours of teaching. Includes helping organize and deliver multiple hands-on courses for programming Intel Xeon Phi, ranging from 2 to 5 day long classes.
Customer and partner visits – numerous technical and business related presentations at events including user group meetings.
Taught sections of parallel programming classes, as a guest lecturer, at multiple universities around the U.S. Also - a guest speaker in college classes in New Zealand, China, Germany, UK, Canada and Mexico.
School visits – classroom visits, especially during National Engineers Week, to motive/excite young minds about engineering.
Parallel Programming for High School Students – Brooklyn Technical High School.
Taught Intel employee development classes on constructive confrontation, situational leadership, dealing with the press at tradeshows; invited speaker at Intel Manager Training courses.
Employment before Intel
Software Project Lead Warp Compilers / GE Radar Systems Division; Syracuse, New York
C and LISP programming, customer training and support
May 1987-February 1989
Teaching Assistant / University of Michigan; Ann Arbors, Michigan
Lectures, grading, labs, office hours; graduate compiler construction, interactive computer graphics, discrete mathematics, data structures, and digital computer engineering lab classes.
September 1983-May 1987
programming summer jobs during high school and college
LISP and C programming; Autonomous Mobile Robot Guidance Systems; 3D modeling and visualization.
General Motors Research, Computer Science; Warren, Michigan / Summers 1986 & 1985